A flash memory is conventionally formed from a plurality of memory cells that can be electrically programed individually, with a large number of cells, called a block, sector or page, able to be erased simultaneously and electrically.
Each flash memory cell is provided with a NMOS transistor comprising a substrate or bulk, source and drain regions formed in the substrate, and a control gate. A conduction channel can be formed in the substrate, between the source and drain regions, according to the bias of the gate of the transistor. This transistor further comprises a site for storing electrical charges, called a floating gate, formed for example of a polysilicon layer arranged between two layers of oxide, and located between the control gate and the conduction channel.
The control gate and the drain of the floating gate transistor are biased differently according to whether it is desired to write, erase or read the memory cell. FIG. 1 is a simplified representation of the signals applied on the control gate and on the drain during the write, erase and read operations of a NOR-type flash memory cell. The bulk and the source are connected to the ground for each one of these operations.
The memory cell can be written to, or programed, by applying simultaneously for 1 μs to 10 μs a high voltage on the control gate, for example between 7 V and 10 V, and a more moderate voltage on the drain of the floating gate transistor, for example between 3 V and 5 V. These voltages allow for the passage of very high energy electrons (referred to as “hot electrons”) from the conduction channel to the floating gate. The electrons are then trapped in the floating gate and cause an increase in the threshold voltage of the transistor. The memory cell thus passes from a “low” or “erased” state, characterised by a low voltage threshold (2 V-4 V), to a “high” or “written” state, characterised by a high voltage threshold (6 V-9 V). In a flash memory cell, one bit of information is therefore encoded by the level of the threshold voltage of the transistor, typically ‘0’ for the low threshold voltage (erased state) and ‘1’ for the high threshold voltage (written state).
The erasing of the memory cell is performed by applying for 1 ms to 200 ms a high negative voltage on the control gate, for example between −10 V and −20 V, while the drain is connected to the ground (zero voltage). This makes it possible to evacuate the electrons trapped in the floating gate, via the tunnel effect through the gate oxide. Thus, the threshold voltage of the transistor is lowered and the memory cell returns to its erased state.
A method for reading the memory cell (i.e. in order to determine its state: written or erased) consists in applying a voltage ramp on the control gate, for example from 0 V to 10 V, while the drain is biased at a voltage of about 0.5 V, and in measuring the drain current during this voltage ramp. Thus, a drain current/gate voltage characteristic is obtained that makes it possible to determine the threshold voltage of the transistor.
In order to evaluate the reliability of the flash memory cell during its technological development, a technique called “endurance measurement” consists in subjecting the memory cell to a multitude of write and erase cycles in a very short lapse of time (in order to accelerate its ageing) and in following the changes in the voltage thresholds of the written state and of erased state over time.
FIG. 2 is an example of curves coming from the endurance measurement of a NOR-type flash memory cell (1T-NOR). These curves show the threshold voltage VT of the transistor in the written state (upper curve) and the threshold voltage VT of the transistor in the erased state (lower curve), according to the number of write/erase cycles that the memory cell was subjected to. A decrease in the threshold voltage VT of the written state and an increase in the threshold voltage VT of the erased state are observed, as the number of write/erase cycles increases. In other words, the programming window, which corresponds to the difference between the two levels of the threshold voltage VT, is reduced as time passes. When this difference decreases below a certain value, for example 3 V, it becomes difficult to distinguish the written state from the erased state and the information stored in the memory cell is lost. This progressive closing of the programming window is linked to an ageing of the gate oxide located between the floating gate and the conduction channel (trapping of electrical charges in the oxide, appearance of defects, etc.).
Each point on the curves of FIG. 2 was obtained by performing a read on the memory cell, after the latter had been written to (for the upper curve) or erased (for the lower curve). The conventional endurance measurement for a flash memory cell therefore consists in applying alternating write and erase signals of the memory cell, and to read from time to time the memory cell in the erased state and in the written state, in order to determine their respective threshold voltage.
FIG. 3 schematically shows a characterisation system that is commonly used to perform this endurance measurement. The memory cell is symbolised by a floating gate transistor 30 provided with four electrodes: the gate G, the drain D, the source S and the bulk B.
The characterisation system comprises a voltage generator 31 able to supply voltages between +20 V and −20 V for a minimum duration of about on microsecond. This generator 31 has a first channel ch1 connected to the gate electrode G of the transistor 30 by the intermediary of a first electromechanical switch 32a and a second channel ch2 connected to the drain electrode D of the transistor 30 by the intermediary of a second electromechanical switch 32b. The generator 31 can thus apply on the electrodes G and D the pulses required to write and erase the memory cell (maximum amplitude equal to 20 V and duration between 1 μs and 200 ms, cf. FIG. 1).
In other terms, the voltage generator 31 controls the writing and erasing operations of the memory cell. However, the generator 31 does not allow to read the memory cell, as it is incapable of measuring the drain current ID according to the voltage VG applied on the gate.
The read operations are therefore performed by means of two Source Measure Units (SMU) 33a and 33b. The output of the SMU 33a is connected to the gate electrode G by the intermediary of the switch 32a, while the output of the SMU 33b is connected to the drain electrode D by the intermediary of the switch 32b. The SMU are instruments that allow to apply a voltage (respectively a current) and to simultaneously measure the corresponding current (respectively the voltage). Here, they are used to simultaneously apply a voltage ramp VG on the gate (VG=0→10 V) and a low voltage VD on the drain (VD=0.5 V), and in order to measure in return the drain current ID. The characteristic ID(VG) is therefore obtained which makes it possible to extract the threshold voltage VT.
Switches 32a and 32b allow, by switching from one position to the other, to couple the electrodes G and D of the transistor 30, either to the generator 31 for the writing and erasing operations, or to the SMU 33a and 33b for the reading operations.
The SMU 33a and 33b are static (or DC) characterisation devices, as they measure the signals during long periods of time, of at least several milliseconds. For example, measuring the drain current ID during the voltage ramp VG can take up to several seconds with such devices. However a static characterisation does not allow for a realistic measurement of the properties of the memory cell. Indeed, the traps created by the ageing of the gate oxide can during the measurement capture and emit charge carriers that modify the electrostatic properties of the cell, resulting in a distortion of the measurement. Inversely, a dynamic characterisation, i.e. in a short lapse of time (typically less than a millisecond), will not leave the time for the traps to capture or release charge carriers and will reflect the intrinsic properties of the memory cell. Dynamic measuring instruments are therefore required in order to more accurately characterise the electrical behaviour of a memory cell.
The apparatuses called PIV (“Pulsed I-V system”) or FMU (“Fast Measurement Unit”) have been sold for this purpose. Mention can be made by way of example of the model “Agilent B1530”. It can generate pulses and voltage ramps while dynamically measuring currents between 1 pA and 10 mA, typically with a sampling duration of about 10 ns. This tool is primarily for electronic devices operating under moderate bias, as the amplitude of the signals delivered is limited to 10 V.
The document [“Impact of endurance degradation on the programming efficiency and the energy consumption of NOR flash memories”, V. Della Marca and al., Microelectronics Reliability, Volume 54, pp. 2262-2265, 2014] proposes a system for the characterisation of NOR-type flash memory cell that makes possible both an endurance test (i.e. a sequence of write and erase cycles), a static measurement of the read current ID(VG) and a dynamic measurement of the write current ID(t) (where t is the write time). This characterisation system is diagrammed in FIG. 4, which uses the nomenclature of FIG. 3.
The characterisation system of the aforementioned document correspond to the characterisation system of FIG. 3, to which two other SMU 33c-33d, a dynamic measurement apparatus (PTV) 34 (Agilent B1530) and three other electromechanical switches with two positions 32c, 32d and 32e have been added. The PTV apparatus 34 comprises three channels ch1, ch2 and ch3 connected respectively to the gate G, drain D, and source S electrodes of the floating gate transistor 30. These connections are carried out by means of switches 32c to 32e, because the electrodes G, D and S also have to be connected to the generator 31 and/or to the SMU 33a to 33c (by the intermediary of switches 32a-32b with regards to the SMU 33a-33b and the generator 31). The outputs of the SMU 33c and 33d are connected respectively to the source electrode S (by the intermediary of the switch 32e) and to the bulk B of the floating gate transistor 30.
Thus, the characterisation system of FIG. 4 comprises three types of instruments connected to the electrodes of the floating gate transistor 30 by the intermediary of two groups of switches. These two groups are comprised of the switches 32a and 32b on the one hand, and of switches 32c to 32e on the other hand. As hereinabove, the generator 31 is in charge of the write and erase operations, while the SMU 33a and 33b proceed with reading the memory cell (measurement ID(VG) in order to extract the threshold voltage). The two additional SMU 33c and 33d are used to bias the electrodes S and B, in order to allow for other write (application of a bias VB on the bulk) or read (measurement of the source current IS according to VG) mechanisms. Finally, the PIV apparatus 34 makes it possible to dynamically measure the drain current ID during a write (in the case where the write operation is performed by the PIV apparatus 34), in order in particular to deduce from it the electrical power consumption of the memory cell. This is then referred to as a “dynamic” write.
Switches 32a to 32e allow to interrupt the write and erase cycles controlled by the generator 31, so that the SMU 33a to 33d can read the memory cell or so that the PIV apparatus 34 can perform a write operation with a dynamic measurement of the drain current ID. They are constituted of electromechanical relays, in order to overcome any parasitic current during the measurement of the drain current ID. On the other hand, this type of switches have long switching times, of around several milliseconds.
FIGS. 5A and 5B show a way of introducing the dynamic read or write operations into an endurance test, thanks to the characterisation system of FIG. 4. The cycles noted C are conventional write and erase cycles, performed by means of the generator 31. Between two of these cycles C, a specific write and erase cycle C′ (FIG. 5A) or C″ (FIG. 5B) is carried out. The cycle C′ comprises a first read after erasing the memory cell and a second read after writing to the memory cell. Two values of the threshold voltage are thus obtained, one in the erased state and the other in the written state. In the cycle C″, the conventional write operation is replaced with a dynamic write operation, in order to have an accurate measurement of the drain current ID and to deduce from it the energy consumed by the write operation. The blocs “DL” located before and after each read in the cycle C′ (FIG. 5A) or before and after each dynamic write in the cycle C″ (FIG. 5B) represent the time required to switch the electromechanical switches 32a-32b (FIG. 5A) or the switches 32c to 32e (FIG. 5B) from one position to the other.
The switching times DL of the electromechanical switches 32a to 32e are not controlled and can distort the electrical characterisation. Indeed, during these time intervals of several milliseconds, the memory cell undergoes an electrostatic relaxation. This results in that the threshold voltage measured during the read is not representative of the written or erased state of the memory cell, but of a relaxed state. An accurate analysis of the reliability of the memory cell is then impossible. Likewise, the measurement of the electrical power consumption coming from the dynamic write of FIG. 5B does not form reliable information on the ageing of the memory cell, also due to the electrostatic relaxation of the memory cell during the switching times DL.
The switching of the electromechanical switches 32a to 32e can furthermore cause voltage peaks that can modify the bias of the cell and therefore its electrical behaviour. These voltage peaks are consequently detrimental to the analysis of reliability.
Finally, since the read operations are performed by the SMU, i.e. statically, the characterisation system of FIG. 4 has the same defect as the characterisation system of FIG. 3, namely a potential distortion of the measurement during the read.